5855 search results - page 352 / 1171 » Test generation and minimization with |
170
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ASPDAC
2004
ACM
16 years 7 days ago
2004
ACM
- Under manufacturing process variation, a path through a fault site is called longest for delay test if there exists a process condition under which the path has the maximum delay...
182
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DATE
2000
IEEE
15 years 11 months ago
2000
IEEE
The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has bee...
191
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FMICS
2008
Springer
15 years 8 months ago
2008
Springer
Lustre is a formal synchronous declarative language widely used for modeling and specifying safety-critical applications in the elds of avionics, transportation or energy productio...
168
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WSC
2000
15 years 8 months ago
2000
What actuaries call cash flow testing is a large-scale simulation pitting a company's current policy obligation against future earnings based on interest rates. While life co...
162
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TII
2008
15 years 6 months ago
2008
This paper presents a novel modeling analysis of jitter as applicable to testing of serial data channels. Jitter is analyzed by considering separate and combined components. The pr...