Sciweavers

5855 search results - page 344 / 1171
» Test generation and minimization with
Sort
View
ICST
2008
IEEE
16 years 1 months ago
On Combining Multi-formalism Knowledge to Select Models for Model Transformation Testing
Testing remains a major challenge for model transformation development. Test models that are used as test data for model transformations, are constrained by various sources of kno...
Sagar Sen, Benoit Baudry, Jean-Marie Mottu
DATE
2007
IEEE
83views Hardware» more  DATE 2007»
16 years 1 months ago
High-level test synthesis for delay fault testability
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...
Sying-Jyan Wang, Tung-Hua Yeh
ETS
2006
IEEE
110views Hardware» more  ETS 2006»
16 years 25 days ago
Deterministic Logic BIST for Transition Fault Testing
BIST is an attractive approach to detect delay faults due to its inherent support for at-speed test. Deterministic logic BIST (DLBIST) is a technique which was successfully applie...
Valentin Gherman, Hans-Joachim Wunderlich, Jü...
143
Voted
DATE
2003
IEEE
93views Hardware» more  DATE 2003»
16 years 2 days ago
Comparison of Test Pattern Decompression Techniques
Test pattern decompression techniques are bounded with the algorithm of test pattern ordering and test data flow controlling. Some of the methods could have more sophisticated sor...
Ondrej Novák
ICECCS
1997
IEEE
114views Hardware» more  ICECCS 1997»
15 years 11 months ago
An approach to integration testing based on architectural descriptions
Software architectures can play a role in improving the testing process of complex systems. In particular, descriptions of the software architecture can be useful to drive integra...
Antonia Bertolino, Paola Inverardi, Henry Muccini,...