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VTS
2002
IEEE
126views Hardware» more  VTS 2002»
15 years 11 months ago
On Using Rectangle Packing for SOC Wrapper/TAM Co-Optimization
The testing time for a system-on-chip (SOC) is determined to a large extent by the design of test wrappers and the test access mechanism (TAM). Wrapper/TAM co-optimization is ther...
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan M...
TCAD
2011
15 years 1 months ago
Low-Power Clock Tree Design for Pre-Bond Testing of 3-D Stacked ICs
—Pre-bond testing of 3-D stacked integrated circuits (ICs) involves testing each individual die before bonding. The overall yield of 3-D ICs improves with pre-bond testability be...
Xin Zhao, Dean L. Lewis, Hsien-Hsin S. Lee, Sung K...
ICST
2010
IEEE
15 years 5 months ago
Automated Behavioral Regression Testing
—When a program is modified during software evolution, developers typically run the new version of the program against its existing test suite to validate that the changes made ...
Wei Jin, Alessandro Orso, Tao Xie
ISQED
2006
IEEE
107views Hardware» more  ISQED 2006»
16 years 22 days ago
On Optimizing Scan Testing Power and Routing Cost in Scan Chain Design
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
Li-Chung Hsu, Hung-Ming Chen
CHI
2010
ACM
16 years 1 months ago
GUI testing using computer vision
Testing a GUI’s visual behavior typically requires human testers to interact with the GUI and to observe whether the expected results of interaction are presented. This paper pr...
Tsung-Hsiang Chang, Tom Yeh, Robert C. Miller