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DFT
2002
IEEE
121views VLSI» more  DFT 2002»
15 years 11 months ago
Testing Digital Circuits with Constraints
Many digital circuits have constraints on the logic values a set of signal lines can have. In this paper, we present two new techniques for detecting the illegal combinations of l...
Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McC...
ATS
1997
IEEE
88views Hardware» more  ATS 1997»
15 years 10 months ago
On the Adders with Minimum Tests
This paper considers two types of n-bit adders, ripple carry adders and cascaded carry look-ahead adders, with minimum tests for stuck-at fault models. In the first part, we prese...
Seiji Kajihara, Tsutomu Sasao
BIOSIG
2003
89views Biometrics» more  BIOSIG 2003»
15 years 8 months ago
How to Test the Performance of Speech Verifiers and Statistical Evaluation
Abstract: Biometric identification and verification technologies, in the past, have promised high performance levels. Such performance statements lead to the assumption, that these...
Jörg Tacke, Andreas Wolf
TIT
1998
78views more  TIT 1998»
15 years 6 months ago
A Detection Optimal Min-Max Test for Transient Signals
—Page’s test is optimal for detecting a permanent change in distribution, in the sense that it minimizes the worst case average delay to detection given an average distance bet...
Chunming Han, Peter K. Willett 0002, Biao Chen, Do...
ICCAD
2009
IEEE
101views Hardware» more  ICCAD 2009»
15 years 4 months ago
Compacting test vector sets via strategic use of implications
As the complexity of integrated circuits has increased, so has the need for improving testing efficiency. Unfortunately, the types of defects are also becoming more complex, which...
Nuno Alves, Jennifer Dworak, R. Iris Bahar, Kundan...