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DSD
2005
IEEE
116views Hardware» more  DSD 2005»
16 years 5 days ago
Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
ATS
2001
IEEE
126views Hardware» more  ATS 2001»
15 years 10 months ago
Design of an Optimal Test Access Architecture Using a Genetic Algorithm
Test access is a major problem for core-based systemon-chip (SOC) designs. Since cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms...
Zahra Sadat Ebadi, André Ivanov
VTS
2000
IEEE
76views Hardware» more  VTS 2000»
15 years 11 months ago
Test Selection Based on High Level Fault Simulation for Mixed-Signal Systems
Mixed-signal design and test tools are failing to keep apace with the increasing necessity for design exploration at the e arly stages.We outline a methodolo gy and toolset to ena...
Sule Ozev, Alex Orailoglu
SAT
2010
Springer
148views Hardware» more  SAT 2010»
15 years 10 months ago
Automated Testing and Debugging of SAT and QBF Solvers
Robustness and correctness are essential criteria for SAT and QBF solvers. We develop automated testing and debugging techniques designed and optimized for SAT and QBF solver devel...
Robert Brummayer, Florian Lonsing, Armin Biere
DATE
2007
IEEE
81views Hardware» more  DATE 2007»
16 years 27 days ago
Using the inter- and intra-switch regularity in NoC switch testing
This paper proposes an efficient test methodology to test switches in a Network-on-Chip (NoC) architecture. A switch in an NoC consists of a number of ports and a router. Using th...
Mohammad Hosseinabady, Atefe Dalirsani, Zainalabed...