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ICCAD
2004
IEEE
127views Hardware» more  ICCAD 2004»
16 years 3 months ago
A yield improvement methodology using pre- and post-silicon statistical clock scheduling
— In deep sub-micron technologies, process variations can cause significant path delay and clock skew uncertainties thereby lead to timing failure and yield loss. In this paper,...
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Pin...
ICCAD
2003
IEEE
127views Hardware» more  ICCAD 2003»
16 years 3 months ago
Code Placement with Selective Cache Activity Minimization for Embedded Real-time Software Design
– Many embedded system designs usually impose (hard) read-time constraints on tasks. Thus, computing a tight upper bound of the worst case execution time (WCET) of a software is ...
Junhyung Um, Taewhan Kim
ICCAD
2002
IEEE
152views Hardware» more  ICCAD 2002»
16 years 3 months ago
Efficient instruction encoding for automatic instruction set design of configurable ASIPs
Application-specific instructions can significantly improve the performance, energy, and code size of configurable processors. A common approach used in the design of such instruc...
Jong-eun Lee, Kiyoung Choi, Nikil Dutt
CVPR
2010
IEEE
16 years 2 months ago
Specular Surface Reconstruction from Sparse Reflection Correspondences
We present a practical approach for surface reconstruction of smooth mirror-like objects using sparse reflection correspondences (RCs). Assuming finite object motion with a fix...
Aswin Sankaranarayanan, Ashok Veeraraghavan, Oncel...
CVPR
2010
IEEE
16 years 2 months ago
Efficiently Selecting Regions for Scene Understanding
Recent advances in scene understanding and related tasks have highlighted the importance of using regions to reason about high-level scene structure. Typically, the regions are ...
M. Pawan Kumar, Daphne Koller