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    ASPDAC
    2004
    ACM
    81views Hardware» more  ASPDAC 2004»
    Technology mapping and packing for coarse-grained, anti-fuse based FPGAs
    15 years 11 months ago
    Technology mapping and packing for coarse-grained, anti-fuse based FPGAs
    Download  atrak.usc.edu
    Chang Woo Kang, Ali Iranli, Massoud Pedram
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    ICCAD
    2007
    IEEE
    164views Hardware» more  ICCAD 2007»
    Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
    16 years 2 months ago
    Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
    Download  www.ee.ucla.edu
    — Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
    Yu Hu, Satyaki Das, Steven Trimberger, Lei He
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