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VLSI
2010
Springer
15 years 4 months ago
Design and feasibility of multi-Gb/s quasi-serial vertical interconnects based on TSVs for 3D ICs
—This paper proposes a novel technique to exploit the high bandwidth offered by through silicon vias (TSVs). In the proposed approach, synchronous parallel 3D links are replaced ...
Fengda Sun, Alessandro Cevrero, Panagiotis Athanas...
HPCA
2005
IEEE
16 years 6 months ago
SENSS: Security Enhancement to Symmetric Shared Memory Multiprocessors
With the increasing concern of the security on high performance multiprocessor enterprise servers, more and more effort is being invested into defending against various kinds of a...
Youtao Zhang, Lan Gao, Jun Yang 0002, Xiangyu Zhan...
JCST
2008
140views more  JCST 2008»
15 years 6 months ago
ROPAS: Cross-Layer Cognitive Architecture for Mobile UWB Networks
The allocation of bandwidth to unlicensed users, without significantly increasing the interference on the existing licensed users, is a challenge for Ultra Wideband (UWB) networks....
Chittabrata Ghosh, Bin Xie, Dharma P. Agrawal
ACMMSP
2005
ACM
101views Hardware» more  ACMMSP 2005»
15 years 11 months ago
Transparent pointer compression for linked data structures
64-bit address spaces are increasingly important for modern applications, but they come at a price: pointers use twice as much memory, reducing the effective cache capacity and m...
Chris Lattner, Vikram S. Adve
VLSID
2002
IEEE
159views VLSI» more  VLSID 2002»
16 years 6 months ago
Challenges in the Design of a Scalable Data-Acquisition and Processing System-on-Silicon
Increasing complexity of the functionalities and the resultant growth in number of gates integrated in a chip coupled with shrinking geometries and short cycle time requirements br...
Karanth Shankaranarayana, Soujanna Sarkar, R. Venk...