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CGO
2004
IEEE
15 years 10 months ago
Targeted Path Profiling: Lower Overhead Path Profiling for Staged Dynamic Optimization Systems
In this paper, we present a technique for reducing the overhead of collecting path profiles in the context of a dynamic optimizer. The key idea to our approach, called Targeted Pa...
Rahul Joshi, Michael D. Bond, Craig B. Zilles
ARCS
2006
Springer
15 years 10 months ago
Combitgen: A new approach for creating partial bitstreams in Virtex-II Pro
Today's FPGAs (Field Programmable Gate Arrays) are widely used, but not to their full potential. In Virtex series FPGAs from Xilinx a special feature, the dynamic and partial...
Christopher Claus, Florian Helmut Müller, Wal...
ARCS
2006
Springer
15 years 10 months ago
Biologically-Inspired Optimization of Circuit Performance and Leakage: A Comparative Study
State-of-the-art technologies in very large scale integration (VLSI) allow for the realization of gates with varying energy consumptions and hence delays (i.e., processing speeds) ...
Ralf Salomon, Frank Sill
CSMR
2004
IEEE
15 years 10 months ago
Rewrite Systems for Symbolic Evaluation of C-like Preprocessing
Automatic analysis of programs with preprocessing directives and conditional compilation is challenging. The difficulties range from parsing to program understanding. Symbolic eva...
Mario Latendresse
CODES
2006
IEEE
15 years 10 months ago
Automatic phase detection for stochastic on-chip traffic generation
During System on Chip (SoC) design, Network on Chip (NoC) prototyping is used for adapting NoC parameters to the application running on the chip. This prototyping is currently don...
Antoine Scherrer, Antoine Fraboulet, Tanguy Risset