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DAC
2005
ACM
16 years 7 months ago
Logic block clustering of large designs for channel-width constrained FPGAs
In this paper we present a system level technique for mapping large, multiple-IP-block designs to channel-width constrained FPGAs. Most FPGA clustering tools [2, 3, 11] aim to red...
Marvin Tom, Guy G. Lemieux
STTT
2010
115views more  STTT 2010»
15 years 4 months ago
Scalable shared memory LTL model checking
Recent development in computer hardware has brought more wide-spread emergence of shared memory, multi-core systems. These architectures offer opportunities to speed up various ta...
Jiri Barnat, Lubos Brim, Petr Rockai
ICC
2007
IEEE
157views Communications» more  ICC 2007»
16 years 21 days ago
Cross-Layer Design of Uplink Multiple-Antenna Interference Cancellation for WLAN with CSMA/CA in Open Access Networks
Abstract— The potential of multi-antenna interference cancellation receiver algorithms for increasing the uplink throughput in WLAN systems such as 802.11 is investigated. The me...
Alexandr M. Kuzminskiy, Hamid Reza Karimi
GROUP
2010
ACM
15 years 4 months ago
Design, implementation, and evaluation of an approach for determining when programmers are having difficulty
Previous research has motivated the idea of automatically determining when programmers are having difficulty, provided an initial algorithm (unimplemented in an actual system), an...
Jason Carter, Prasun Dewan
COMPSAC
2002
IEEE
15 years 11 months ago
A Graphically Based Language for Constructing, Executing and Analysing Models of Software Systems
With computer systems becoming ever larger and more complex, the cost and effort associated with their construction is increasing and the systems are now sufficiently complex that...
Robert John Walters