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ISCA
1999
IEEE
124views Hardware» more  ISCA 1999»
15 years 10 months ago
Speculation Techniques for Improving Load Related Instruction Scheduling
State of the art microprocessors achieve high performance by executing multiple instructions per cycle. In an out-oforder engine, the instruction scheduler is responsible for disp...
Adi Yoaz, Mattan Erez, Ronny Ronen, Stéphan...
TON
2008
155views more  TON 2008»
15 years 6 months ago
A comparative analysis of server selection in content replication networks
Server selection plays an essential role in content replication networks, such as peer-to-peer (P2P) and content delivery networks (CDNs). In this paper, we perform an analytical i...
Tao Wu, David Starobinski
DATE
2008
IEEE
75views Hardware» more  DATE 2008»
16 years 24 days ago
A low-cost concurrent error detection technique for processor control logic
This paper presents a concurrent error detection technique targeted towards control logic in a processor with emphasis on low area overhead. Rather than detect all modeled transie...
Ramtilak Vemu, Abhijit Jas, Jacob A. Abraham, Srin...
NSDI
2004
15 years 7 months ago
Designing a DHT for Low Latency and High Throughput
Designing a wide-area distributed hash table (DHT) that provides high-throughput and low-latency network storage is a challenge. Existing systems have explored a range of solution...
Frank Dabek, Jinyang Li, Emil Sit, James Robertson...
SIGOPSE
2004
ACM
15 years 11 months ago
Scalable strong consistency for web applications
Web application workloads are often characterized by a large number of unique read requests and a significant fraction of write requests. Hosting these applications drives the ne...
Swaminathan Sivasubramanian, Guillaume Pierre, Maa...