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SAT
2010
Springer
174views Hardware» more  SAT 2010»
15 years 5 months ago
A System for Solving Constraint Satisfaction Problems with SMT
Abstract. SAT Modulo Theories (SMT) consists of deciding the satisfiability of a formula with respect to a decidable background theory, such as linear integer arithmetic, bit-vect...
Miquel Bofill, Josep Suy, Mateu Villaret
CADE
2008
Springer
16 years 7 months ago
Certifying a Tree Automata Completion Checker
Tree automata completion is a technique for the verification of infinite state systems. It has already been used for the verification of cryptographic protocols and the prototyping...
Benoît Boyer, Thomas Genet, Thomas P. Jensen
ISLPED
2009
ACM
125views Hardware» more  ISLPED 2009»
16 years 1 months ago
Behavior-level observability don't-cares and application to low-power behavioral synthesis
Many techniques for power management employed in advanced RTL synthesis tools rely explicitly or implicitly on observability don’t-care (ODC) conditions. In this paper we presen...
Jason Cong, Bin Liu, Zhiru Zhang
CGF
2008
103views more  CGF 2008»
15 years 6 months ago
An Example-based Procedural System for Element Arrangement
We present a method for synthesizing two dimensional (2D) element arrangements from an example. The main idea is to combine texture synthesis techniques based-on a local neighborh...
Takashi Ijiri, Radomír Mech, Takeo Igarashi...
VLSID
1999
IEEE
93views VLSI» more  VLSID 1999»
15 years 11 months ago
Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect
Recently Lillis, et al. presented an elegant dynamic programming approach to RC interconnect delay optimization through driver sizing, repeater insertion, and, wire sizing which e...
Noel Menezes, Chung-Ping Chen