Sciweavers

3340 search results - page 507 / 668
» Teaching networking hardware
Sort
View
ACSD
2003
IEEE
151views Hardware» more  ACSD 2003»
16 years 15 days ago
Communicating Transaction Processes
Message Sequence Charts (MSC) have been traditionally used to depict execution scenarios in the early stages of design cycle. MSCs portray inter-process ( inter-object) interactio...
Abhik Roychoudhury, P. S. Thiagarajan
DATE
2003
IEEE
96views Hardware» more  DATE 2003»
16 years 15 days ago
Time Domain Multiplexed TAM: Implementation and Comparison
One of the difficult problems which core-based systemon-chip (SoC) designs face is test access. For testing the cores in a SoC, a special mechanism is required, since they are no...
Zahra Sadat Ebadi, André Ivanov
ISCA
2003
IEEE
101views Hardware» more  ISCA 2003»
16 years 14 days ago
Overcoming the Limitations of Conventional Vector Processors
Despite their superior performance for multimedia applications, vector processors have three limitations that hinder their widespread acceptance. First, the complexity and size of...
Christoforos E. Kozyrakis, David A. Patterson
SBACPAD
2003
IEEE
180views Hardware» more  SBACPAD 2003»
16 years 14 days ago
New Parallel Algorithms for Frequent Itemset Mining in Very Large Databases
Frequent itemset mining is a classic problem in data mining. It is a non-supervised process which concerns in finding frequent patterns (or itemsets) hidden in large volumes of d...
Adriano Veloso, Wagner Meira Jr., Srinivasan Parth...
SBACPAD
2003
IEEE
125views Hardware» more  SBACPAD 2003»
16 years 14 days ago
Applying Scheduling by Edge Reversal to Constraint Partitioning
— Scheduling by Edge Reversal (SER) is a fully distributed scheduling mechanism based on the manipulation of acyclic orientations of a graph. This work uses SER to perform constr...
Marluce Rodrigues Pereira, Patrícia Kayser ...