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MICRO
2009
IEEE
124views Hardware» more  MICRO 2009»
16 years 1 months ago
ZerehCache: armoring cache architectures in high defect density technologies
Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Large SRAM structures used for caches are particularly ...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
ISCA
2007
IEEE
110views Hardware» more  ISCA 2007»
16 years 1 months ago
Late-binding: enabling unordered load-store queues
Conventional load/store queues (LSQs) are an impediment to both power-efficient execution in superscalar processors and scaling to large-window designs. In this paper, we propose...
Simha Sethumadhavan, Franziska Roesner, Joel S. Em...
SECON
2007
IEEE
16 years 1 months ago
A SoC-based Sensor Node: Evaluation of RETOS-enabled CC2430
—Recent progress in Wireless Sensor Networks technology has enabled many complicated real-world applications. Some of the applications demand a non-trivial amount of computation;...
Sukwon Choi, Hojung Cha, SungChil Cho
EENERGY
2010
15 years 11 months ago
Statistical static capacity management in virtualized data centers supporting fine grained QoS specification
From an ecological but also from an economical and in the meantime a technical view the fast ongoing increase of power consumption in today’s data centers is no longer feasible....
Marko Hoyer, Kiril Schröder, Wolfgang Nebel
ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
15 years 7 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri