Sciweavers

3340 search results - page 442 / 668
» Teaching networking hardware
Sort
View
DATE
2006
IEEE
82views Hardware» more  DATE 2006»
16 years 1 months ago
Performance analysis of greedy shapers in real-time systems
— Traffic shaping is a well-known technique in the area of networking and is proven to reduce global buffer requirements and end-to-end delays in networked systems. Due to these...
Ernesto Wandeler, Alexander Maxiaguine, Lothar Thi...
DSD
2006
IEEE
159views Hardware» more  DSD 2006»
16 years 1 months ago
Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions
Region concept helps to accommodate cores larger than the tile size in mesh topology NoC architectures. In addition, it offers many new opportunities for NoC design, as well as pr...
Rickard Holsmark, Maurizio Palesi, Shashi Kumar
DSN
2006
IEEE
16 years 1 months ago
Automatic Instruction-Level Software-Only Recovery
As chip densities and clock rates increase, processors are becoming more susceptible to transient faults that can affect program correctness. Computer architects have typically ad...
Jonathan Chang, George A. Reis, David I. August
ECBS
2006
IEEE
126views Hardware» more  ECBS 2006»
16 years 1 months ago
Experiments and Investigations for the Personal High Performance Computing (PHPC) built on top of the 64-bit processing and clus
The motivation and objective for this paper is to demonstrate “Personal High Performance Computing (PHPC)”, which requires only a smaller number of computers, resources and sp...
Victor Chang
ETS
2006
IEEE
108views Hardware» more  ETS 2006»
16 years 1 months ago
A DFT Architecture for Asynchronous Networks-on-Chip
The Networks-on-Chip (NoCs) paradigm is emerging as a solution for the communication of SoCs. Many NoC architecture propositions are presented but few works on testing these netwo...
Xuan-Tu Tran, Jean Durupt, François Bertran...