3340 search results - page 376 / 668 » Teaching networking hardware |
221
click to vote
DATE
2007
IEEE
16 years 1 months ago
2007
IEEE
The majority of current Network on Chip (NoC) architectures employ mesh topology and use simple static routing, to reduce power and area. However, regular mesh topology is unreali...
227
click to vote
CSREAESA
2006
15 years 8 months ago
2006
The Satellite Data Model (SDM) is part of the Air Force Research Laboratory (AFRL) Responsive Space Testbed Initiative. It is a developing standard for rapid integration of hardwa...
174
click to vote
ICCD
2004
IEEE
16 years 3 months ago
2004
IEEE
In this paper, we investigate the core-switch mapping(CSM) problem that optimally maps cores onto an NoC architecture such that either the energy consumption or the congestion is ...
170
click to vote
ICCD
2004
IEEE
16 years 3 months ago
2004
IEEE
A cache access time model, PRACTICS (PRedictor of Access and Cycle TIme for Cache Stack), has been developed to optimize the memory array architecture for the minimum access and c...
149
click to vote
ICCD
2003
IEEE
16 years 3 months ago
2003
IEEE
The VLIW processors with static instruction scheduling and thus deterministic execution times are very suitable for highperformance real-time DSP applications. But the two major w...