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DATE
2003
IEEE
132views Hardware» more  DATE 2003»
16 years 1 days ago
Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design
On-chip communication design includes designing software (SW) parts (operating system, device drivers, interrupt service routines, etc.) as well as hardware (HW) parts (on-chip co...
Youngchul Cho, Ganghee Lee, Sungjoo Yoo, Kiyoung C...
FPL
2009
Springer
156views Hardware» more  FPL 2009»
15 years 11 months ago
A highly scalable Restricted Boltzmann Machine FPGA implementation
Restricted Boltzmann Machines (RBMs) — the building block for newly popular Deep Belief Networks (DBNs) — are a promising new tool for machine learning practitioners. However,...
Sang Kyun Kim, Lawrence C. McAfee, Peter L. McMaho...
WAN
1998
Springer
15 years 11 months ago
ParaStation User Level Communication
PULC is a user-level communication library for workstation clusters. PULC provides a multi-user, multi-programming communication library for user level communication on top of high...
Joachim M. Blum, Thomas M. Warschko, Walter F. Tic...
SI3D
1992
ACM
15 years 10 months ago
Interactive Volume Rendering on a Multicomputer
Direct volume rendering is a computationally intensive operation that has become a valued and often preferred visualization tool. For maximal data comprehension, interactive manip...
Ulrich Neumann
FPL
2006
Springer
242views Hardware» more  FPL 2006»
15 years 10 months ago
TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs
With current FPGAs, designers can now instantiate several embedded processors, memory units, and a wide variety of IP blocks to build a single-chip, high-performance multiprocesso...
Manuel Saldaña, Paul Chow