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MICRO
2010
IEEE
156views Hardware» more  MICRO 2010»
15 years 5 months ago
Explicit Communication and Synchronization in SARC
SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible...
Manolis Katevenis, Vassilis Papaefstathiou, Stamat...
ARC
2009
Springer
140views Hardware» more  ARC 2009»
16 years 1 months ago
FPGA-Based Anomalous Trajectory Detection Using SOFM
A system for automatically classifying the trajectory of a moving object in a scene as usual or suspicious is presented. The system uses an unsupervised neural network (Self Organi...
Kofi Appiah, Andrew Hunter, Tino Kluge, Philip Aik...
DSN
2007
IEEE
16 years 1 months ago
Using Process-Level Redundancy to Exploit Multiple Cores for Transient Fault Tolerance
Transient faults are emerging as a critical concern in the reliability of general-purpose microprocessors. As architectural trends point towards multi-threaded multi-core designs,...
Alex Shye, Tipp Moseley, Vijay Janapa Reddi, Josep...
MIDDLEWARE
2004
Springer
16 years 3 days ago
Data pipelines: enabling large scale multi-protocol data transfers
Collaborating users need to move terabytes of data among their sites, often involving multiple protocols. This process is very fragile and involves considerable human involvement ...
Tevfik Kosar, George Kola, Miron Livny
CODES
2003
IEEE
16 years 1 days ago
Programmers' views of SoCs
System-on-chip (SoC) designs have the potential to change the way we organize computation. This potential has gone unrealized. Future SoCs will have multiple heterogeneous process...
JoAnn M. Paul