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DSD
2007
IEEE
160views Hardware» more  DSD 2007»
16 years 1 months ago
Alternatives in Designing Level-Restoring Buffers for Interconnection Networks in Field-Programmable Gate Arrays
Programmable routing and logic in field-programmable gate arrays are implemented using nMOS pass transistors. Since the threshold voltage drop across an nMOS device degrades the ...
Scott Miller, Mihai Sima, Michael McGuire
ISQED
2007
IEEE
127views Hardware» more  ISQED 2007»
16 years 1 months ago
Sensitivity Based Link Insertion for Variation Tolerant Clock Network Synthesis
Clock distribution is one of the key limiting factors in any high speed, sub-100nm VLSI design. Unwanted clock skews, caused by variation effects like manufacturing variations, po...
Joon-Sung Yang, Anand Rajaram, Ninghy Shi, Jian Ch...
MSS
2000
IEEE
160views Hardware» more  MSS 2000»
15 years 11 months ago
Implementation of a Fault-Tolerant Real-Time Network-Attached Storage Device
Phoenix is a fault-tolerantreal-time network-attachedstorage device (NASD). Like other NASD architectures, Phoenix provides an object-based interface to data stored on network-att...
Ashish Raniwala, Srikant Sharma, Anindya Neogi, Tz...
ICCAD
2007
IEEE
119views Hardware» more  ICCAD 2007»
15 years 8 months ago
IntSim: A CAD tool for optimization of multilevel interconnect networks
– Interconnect issues are becoming increasingly important for ULSI systems. IntSim, an interconnect CAD tool, has been developed to obtain pitches of different wiring levels and ...
Deepak C. Sekar, Azad Naeemi, Reza Sarvari, Jeffre...
IEEEPACT
1998
IEEE
15 years 11 months ago
Sirocco: Cost-Effective Fine-Grain Distributed Shared Memory
Software fine-grain distributed shared memory (FGDSM) provides a simplified shared-memory programming interface with minimal or no hardware support. Originally software FGDSMs tar...
Ioannis Schoinas, Babak Falsafi, Mark D. Hill, Jam...