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ISCA
1996
IEEE
99views Hardware» more  ISCA 1996»
15 years 11 months ago
Coherent Network Interfaces for Fine-Grain Communication
Historically, processor accesses to memory-mapped device registers have been marked uncachable to insure their visibility to the device. The ubiquity of snooping cache coherence, ...
Shubhendu S. Mukherjee, Babak Falsafi, Mark D. Hil...
ISCA
1993
IEEE
117views Hardware» more  ISCA 1993»
15 years 11 months ago
Evaluation of Release Consistent Software Distributed Shared Memory on Emerging Network Technology
We evaluate the e ect of processor speed, network bandwidth, and software overhead on the performance of release-consistent software distributed shared memory. We examine ve di er...
Sandhya Dwarkadas, Peter J. Keleher, Alan L. Cox, ...
MST
2011
200views Hardware» more  MST 2011»
15 years 1 months ago
Performance of Scheduling Policies in Adversarial Networks with Non-synchronized Clocks
In this paper we generalize the Continuous Adversarial Queuing Theory (CAQT) model [5] by considering the possibility that the router clocks in the network are not synchronized. W...
Antonio Fernández Anta, José Luis L&...
ICCAD
2008
IEEE
122views Hardware» more  ICCAD 2008»
16 years 3 months ago
Network flow-based power optimization under timing constraints in MSV-driven floorplanning
Abstract— Power consumption has become a crucial problem in modern circuit design. Multiple Supply Voltage (MSV) design is introduced to provide higher flexibility in controllin...
Qiang Ma, Evangeline F. Y. Young
DSD
2009
IEEE
118views Hardware» more  DSD 2009»
16 years 1 months ago
Internet-Router Buffered Crossbars Based on Networks on Chip
—The scalability and performance of the Internet depends critically on the performance of its packet switches. Current packet switches are based on single-hop crossbar fabrics, w...
Kees Goossens, Lotfi Mhamdi, Iria Varela Senin