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DATE
2009
IEEE
183views Hardware» more  DATE 2009»
16 years 1 months ago
SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips
Three-dimensional integrated circuits are a promising approach to address the integration challenges faced by current Systems on Chips (SoCs). Designing an efficient Network on C...
Ciprian Seiculescu, Srinivasan Murali, Luca Benini...
MICRO
2009
IEEE
121views Hardware» more  MICRO 2009»
16 years 1 months ago
Application-aware prioritization mechanisms for on-chip networks
Network-on-Chips (NoCs) are likely to become a critical shared resource in future many-core processors. The challenge is to develop policies and mechanisms that enable multiple ap...
Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chi...
ICCAD
1997
IEEE
69views Hardware» more  ICCAD 1997»
15 years 11 months ago
Speeding up technology-independent timing optimization by network partitioning
Technology-independenttimingoptimizationis animportantproblem in logic synthesis. Although many promising techniques have been proposed in the past, unfortunately they are quite s...
Rajat Aggarwal, Rajeev Murgai, Masahiro Fujita
ICCAD
1995
IEEE
134views Hardware» more  ICCAD 1995»
15 years 10 months ago
A delay model for logic synthesis of continuously-sized networks
ng certain electrical noise and power constraints.Abstract: We present a new delay model for use in logic synthesis. A traditional model treats the area of a library cell as consta...
Joel Grodstein, Eric Lehman, Heather Harkness, Bil...
JNW
2008
111views more  JNW 2008»
15 years 6 months ago
Wireless Sensor Network for Wearable Physiological Monitoring
Wearable physiological monitoring system consists of an array of sensors embedded into the fabric of the wearer to continuously monitor the physiological parameters and transmit wi...
Poondi Srinivasan Pandian, Kadavath Peedikayil Saf...