Sciweavers

3340 search results - page 294 / 668
» Teaching networking hardware
Sort
View
DCOSS
2005
Springer
16 years 7 days ago
Using Clustering Information for Sensor Network Localization
Sensor network localization continues to be an important research challenge. The goal of localization is to assign geographic coordinates to each node in the sensor network. Locali...
Haowen Chan, Mark Luk, Adrian Perrig
ICANN
2005
Springer
16 years 7 days ago
A Real-Time, FPGA Based, Biologically Plausible Neural Network Processor
Abstract. A real-time, large scale, leaky-integrate-and-fire neural network processor realized using FPGA is presented. This has been designed, as part of a collaborative project,...
Martin J. Pearson, Ian Gilhespy, Kevin N. Gurney, ...
PEWASUN
2004
ACM
16 years 4 days ago
A routing protocol for power constrained networks with asymmetric links
In many instances, an ad hoc network consists of nodes with different hardware and software capabilities as well as power limitations. This is the case of ad hoc grids where devi...
Guoqiang Wang, Yongchang Ji, Dan C. Marinescu, Dam...
GLVLSI
2003
IEEE
175views VLSI» more  GLVLSI 2003»
16 years 2 hour ago
A custom FPGA for the simulation of gene regulatory networks
We present a unique FPGA that uses a mix of digital and large-signal analog computation for the simulation of gene regulatory networks. The prototype IC consists of a 4x5 array of...
Ilias Tagkopoulos, Charles A. Zukowski, German Cav...
ISLPED
2003
ACM
83views Hardware» more  ISLPED 2003»
15 years 12 months ago
Leakage power modeling and optimization in interconnection networks
Power will be the key limiter to system scalability as interconnection networks take up an increasingly significant portion of system power. In this paper, we propose an architec...
Xuning Chen, Li-Shiuan Peh