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ISQED
2007
IEEE
109views Hardware» more  ISQED 2007»
16 years 29 days ago
Virtual Channels Planning for Networks-on-Chip
The virtual channel flow control (VCFC) provides an efficient implementation for on-chip networks. However, allocating the virtual channels (VCs) uniformly results in a waste of a...
Ting-Chun Huang, Ümit Y. Ogras, Radu Marcules...
FPL
2007
Springer
126views Hardware» more  FPL 2007»
16 years 25 days ago
A Time-Triggered Network-on-Chip
In this paper we propose a time-triggered network-onchip (NoC) for on-chip real-time systems. The NoC provides time predictable on- and off-chip communication, a mandatory feature...
Martin Schoeberl
DATE
2006
IEEE
149views Hardware» more  DATE 2006»
16 years 22 days ago
Communication architecture optimization: making the shortest path shorter in regular networks-on-chip
Network-on-Chip (NoC)-based communication represents a promising solution to complex on-chip communication problems. Due to their regular structure, mesh-like NoC architectures ha...
Ümit Y. Ogras, Radu Marculescu, Hyung Gyu Lee...
ICCAD
2006
IEEE
132views Hardware» more  ICCAD 2006»
16 years 21 days ago
Clock buffer polarity assignment for power noise reduction
Abstract—Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polariti...
Rupak Samanta, Ganesh Venkataraman, Jiang Hu
DATE
2005
IEEE
97views Hardware» more  DATE 2005»
16 years 9 days ago
Efficient Solution of Language Equations Using Partitioned Representations
A class of discrete event synthesis problems can be reduced to solving language equations F • X ⊆ S, where F is the fixed component and S the specification. Sequential synthes...
Alan Mishchenko, Robert K. Brayton, Jie-Hong Rolan...