3340 search results - page 252 / 668 » Teaching networking hardware |
146
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DATE
2002
IEEE
15 years 11 months ago
2002
IEEE
We present a new passive model reduction algorithm based on the Laguerre expansion of the time response of interconnect networks. We derive expressions for the Laguerre coefficie...
160
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DATE
2002
IEEE
15 years 11 months ago
2002
IEEE
We consider the implication of deep sub-micron VLSI technology on the design of communication frameworks for parallel DSP systems-on-chip. We assert that distributed data transfer...
168
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ASYNC
2000
IEEE
15 years 11 months ago
2000
IEEE
In this paper we describe a complete design methodology for a globally asynchronous onchip communication network connecting both locally-synchronous and asynchronous modules. Sync...
157
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ECBS
2000
IEEE
15 years 11 months ago
2000
IEEE
Quantitative techniques have traditionally been used to assess software architectures. We have found that early in the development process there is often insufficient quantitative...
187
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ICCAD
2000
IEEE
15 years 11 months ago
2000
IEEE
In this paper, we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provi...