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GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
15 years 11 months ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
ISCA
2010
IEEE
181views Hardware» more  ISCA 2010»
15 years 11 months ago
ColorSafe: architectural support for debugging and dynamically avoiding multi-variable atomicity violations
In this paper, we propose ColorSafe, an architecture that detects and dynamically avoids single- and multi-variable atomicity violation bugs. The key idea is to group related data...
Brandon Lucia, Luis Ceze, Karin Strauss
ISCA
2010
IEEE
185views Hardware» more  ISCA 2010»
15 years 11 months ago
Dynamic warp subdivision for integrated branch and memory divergence tolerance
SIMD organizations amortize the area and power of fetch, decode, and issue logic across multiple processing units in order to maximize throughput for a given area and power budget...
Jiayuan Meng, David Tarjan, Kevin Skadron
CF
2010
ACM
15 years 11 months ago
Load balancing using dynamic cache allocation
Supercomputers need a huge budget to be built and maintained. To maximize the usage of their resources, application developers spend time to optimize the code of the parallel appl...
Miquel Moretó, Francisco J. Cazorla, Rizos ...
CLOUD
2010
ACM
15 years 11 months ago
A self-organized, fault-tolerant and scalable replication scheme for cloud storage
Failures of any type are common in current datacenters, partly due to the higher scales of the data stored. As data scales up, its availability becomes more complex, while differe...
Nicolas Bonvin, Thanasis G. Papaioannou, Karl Aber...
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