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» Systems Design, Process Performance and Economic Outcomes
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ISCA
2007
IEEE
111views Hardware» more  ISCA 2007»
16 years 20 days ago
Express virtual channels: towards the ideal interconnection fabric
Due to wire delay scalability and bandwidth limitations inherent in shared buses and dedicated links, packet-switched on-chip interconnection networks are fast emerging as the per...
Amit Kumar 0002, Li-Shiuan Peh, Partha Kundu, Nira...
ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
16 years 12 days ago
Multiple Instruction Stream Processor
Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallel...
Richard A. Hankins, Gautham N. Chinya, Jamison D. ...
ISCA
2000
IEEE
103views Hardware» more  ISCA 2000»
15 years 10 months ago
Piranha: a scalable architecture based on single-chip multiprocessing
The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limit...
Luiz André Barroso, Kourosh Gharachorloo, R...
CORR
2008
Springer
88views Education» more  CORR 2008»
15 years 6 months ago
Framework for Dynamic Evaluation of Muscle Fatigue in Manual Handling Work
- Muscle fatigue is defined as the point at which the muscle is no longer able to sustain the required force or work output level. The overexertion of muscle force and muscle fatig...
Liang Ma, Fouad Bennis, Damien Chablat, Wei Zhang
PPOPP
2009
ACM
16 years 7 months ago
Efficient and scalable multiprocessor fair scheduling using distributed weighted round-robin
Fairness is an essential requirement of any operating system scheduler. Unfortunately, existing fair scheduling algorithms are either inaccurate or inefficient and non-scalable fo...
Tong Li, Dan P. Baumberger, Scott Hahn