5744 search results - page 848 / 1149 » System level design, a VHDL based approach |
194
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DSD
2004
IEEE
15 years 10 months ago
2004
IEEE
Validation of programmable architectures, consisting of processor cores, coprocessors, and memory subsystems, is one of the major bottlenecks in current Systemon-Chip design metho...
172
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FASE
1998
Springer
15 years 11 months ago
1998
Springer
A critical issue for complex component-based systems design is the modeling and analysis of architecture. One of the complicating factors in developing architectural models is acc...
209
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CODES
2006
IEEE
16 years 26 days ago
2006
IEEE
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
157
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VTC
2006
IEEE
16 years 24 days ago
2006
IEEE
— In this paper, a semi-analytical approach for the performance analysis of the random time slot (TS) hopping (RTSH) algorithm applied to code division multiple access time divis...
181
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WEBI
2005
Springer
16 years 8 days ago
2005
Springer
We present a generic natural language processing (NLP) architecture, acronym QTIL, based on a system of cooperating multiple agents (Q/A, T, I, and L agents) which can be used in ...