5744 search results - page 81 / 1149 » System level design, a VHDL based approach |
184
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ICCAD
1995
IEEE
15 years 9 months ago
1995
IEEE
In this paper we investigate activity-driven clock trees to reduce the dynamic power consumption of synchronous digital CMOS circuits. Sections of an activity-driven clock tree ca...
157
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DATE
2010
IEEE
15 years 10 months ago
2010
IEEE
-- Starting Electronic System Level (ESL) design flows with executable High-Level Models (HLMs) has the potential to sustainably improve productivity. However, writing good HLMs fo...
148
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CODES
2001
IEEE
15 years 9 months ago
2001
IEEE
This paper presents a practical approach to communication synthesis for hardware/software system specified as tasks communicating through lossless blocking channels. It relies on ...
232
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FPT
2005
IEEE
15 years 11 months ago
2005
IEEE
We describe a communication-centric design methodology with SystemC that allows for efficient FPGA prototype generation of transaction level models (TLM). Using a framework compr...
251
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WETICE
1997
IEEE
15 years 10 months ago
1997
IEEE
Contemporary product design and process development is based on an iterative specify-evaluate-revise approach which is often time intensive and therein non-responsive to customer ...