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» System level design, a VHDL based approach
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231
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JMLR
2011
192views more  JMLR 2011»
15 years 1 months ago
Minimum Description Length Penalization for Group and Multi-Task Sparse Learning
We propose a framework MIC (Multiple Inclusion Criterion) for learning sparse models based on the information theoretic Minimum Description Length (MDL) principle. MIC provides an...
Paramveer S. Dhillon, Dean P. Foster, Lyle H. Unga...
224
Voted
CODES
2004
IEEE
15 years 10 months ago
A loop accelerator for low power embedded VLIW processors
The high transistor density afforded by modern VLSI processes have enabled the design of embedded processors that use clustered execution units to deliver high levels of performan...
Binu K. Mathew, Al Davis
172
Voted
ISLPED
2004
ACM
123views Hardware» more  ISLPED 2004»
16 years 9 days ago
An efficient voltage scaling algorithm for complex SoCs with few number of voltage modes
Increasing demand for larger high-performance applications requires developing more complex systems with hundreds of processing cores on a single chip. To allow dynamic voltage sc...
Bita Gorjiara, Nader Bagherzadeh, Pai H. Chou
IEEEARES
2007
IEEE
16 years 1 months ago
Compartmented Security for Browsers - Or How to Thwart a Phisher with Trusted Computing
Identity theft through phishing attacks has become a major concern for Internet users. Typically, phishing attacks aim at luring the user to a faked web site to disclose personal ...
Sebastian Gajek, Ahmad-Reza Sadeghi, Christian St&...
SECON
2007
IEEE
16 years 1 months ago
Experimental Investigation of IEEE 802.15.4 Transmission Power Control and Interference Minimization
Abstract—Although the characteristics of RF transmissions are physically well understood at the lowest levels of communication design, accurately incorporating power and interfer...
Steven Myers, Seapahn Megerian, Suman Banerjee, Mi...