Sciweavers

5744 search results - page 635 / 1149
» System level design, a VHDL based approach
Sort
View
TPDS
2010
174views more  TPDS 2010»
15 years 5 months ago
Parallel Two-Sided Matrix Reduction to Band Bidiagonal Form on Multicore Architectures
The objective of this paper is to extend, in the context of multicore architectures, the concepts of tile algorithms [Buttari et al., 2007] for Cholesky, LU, QR factorizations to t...
Hatem Ltaief, Jakub Kurzak, Jack Dongarra
CC
2008
Springer
240views System Software» more  CC 2008»
15 years 9 months ago
Hardware JIT Compilation for Off-the-Shelf Dynamically Reconfigurable FPGAs
JIT compilation is a model of execution which translates at run time critical parts of the program to a low level representation. Typically a JIT compiler produces machine code fro...
Etienne Bergeron, Marc Feeley, Jean-Pierre David
TAICPART
2006
IEEE
134views Education» more  TAICPART 2006»
16 years 1 months ago
Integration Testing of Components Guided by Incremental State Machine Learning
The design of complex systems, e.g., telecom services, is nowadays usually based on the integration of components (COTS), loosely coupled in distributed architectures. When compon...
Keqin Li 0002, Roland Groz, Muzammil Shahbaz
IJON
2011
90views more  IJON 2011»
14 years 10 months ago
Fault tolerant machine learning for nanoscale cognitive radio
We introduce a machine learning based classifier that identifies free radio channels for cognitive radio. The architecture is designed for nanoscale implementation, under nanosc...
Joni Pajarinen, Jaakko Peltonen, Mikko A. Uusitalo
CSCL
2006
109views more  CSCL 2006»
15 years 7 months ago
Supporting synchronous collaborative learning: A generic, multi-dimensional model
Future CSCL technologies are described by the community as flexible, tailorable, negotiable, and appropriate for various collaborative settings, conditions and contexts. This paper...
Jacques Lonchamp