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» System level design, a VHDL based approach
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CODES
2006
IEEE
15 years 11 months ago
Increasing hardware efficiency with multifunction loop accelerators
To meet the conflicting goals of high-performance low-cost embedded systems, critical application loop nests are commonly executed on specialized hardware accelerators. These loop...
Kevin Fan, Manjunath Kudlur, Hyunchul Park, Scott ...
ICC
2007
IEEE
124views Communications» more  ICC 2007»
16 years 1 months ago
On the Performance of IEEE 802.16 OFDMA System Under Different Frequency Reuse and Subcarrier Permutation Patterns
— In interference-limited wireless cellular systems, interference avoidance and interference averaging are widely adopted to combat co-channel interference. In different types of...
Huiling Jia, Zhaoyang Zhang, Guanding Yu, Peng Che...
VLSISP
2008
239views more  VLSISP 2008»
15 years 7 months ago
An Embedded Real-Time Surveillance System: Implementation and Evaluation
This paper presents the design of an embedded automated digital video surveillance system with real-time performance. Hardware accelerators for video segmentation, morphological op...
Fredrik Kristensen, Hugo Hedberg, Hongtu Jiang, Pe...
CHES
2009
Springer
265views Cryptology» more  CHES 2009»
16 years 8 months ago
Higher-Order Masking and Shuffling for Software Implementations of Block Ciphers
Differential Power Analysis (DPA) is a powerful side channel key recovery attack that efficiently breaks block ciphers implementations. In software, two main techniques are usually...
Matthieu Rivain, Emmanuel Prouff, Julien Doget
ATVA
2007
Springer
136views Hardware» more  ATVA 2007»
16 years 1 months ago
Symbolic Fault Tree Analysis for Reactive Systems
Fault tree analysis is a traditional and well-established technique for analyzing system design and robustness. Its purpose is to identify sets of basic events, called cut sets, wh...
Marco Bozzano, Alessandro Cimatti, Francesco Tappa...