5744 search results - page 140 / 1149 » System level design, a VHDL based approach |
191
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CCS
2009
ACM
15 years 10 months ago
2009
ACM
We present an approach for the design and analysis of an electronic voting machine based on a novel combination of formal verification and systematic testing. The system was desig...
209
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FMCAD
2006
Springer
15 years 10 months ago
2006
Springer
The importance of re-usable Intellectual Properties (IPs) cores is increasing due to the growing complexity of today's system-on-chip and the need for rapid prototyping. In th...
152
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COMCOM
2000
15 years 6 months ago
2000
ABSTRACT -- SPEC-VALUE, a rigorous scenario-driven approach for the description and validation of complex system functionalities at the early stages of design, is presented. It is ...
169
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DAC
2006
ACM
16 years 7 months ago
2006
ACM
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
152
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DATE
2007
IEEE
16 years 21 days ago
2007
IEEE
This paper proposes an innovative methodology to perform and validate a Failure Mode and Effects Analysis (FMEA) at System-on-Chip (SoC) level. This is done in compliance with the...