Sciweavers

15155 search results - page 2726 / 3031
» System Software
Sort
View
CGO
2008
IEEE
16 years 1 months ago
Prediction and trace compression of data access addresses through nested loop recognition
This paper describes an algorithm that takes a trace (i.e., a sequence of numbers or vectors of numbers) as input, and from that produces a sequence of loop nests that, when run, ...
Alain Ketterlin, Philippe Clauss
CODES
2008
IEEE
16 years 1 months ago
Don't forget memories: a case study redesigning a pattern counting ASIC circuit for FPGAs
Modern embedded compute platforms increasingly contain both microprocessors and field-programmable gate arrays (FPGAs). The FPGAs may implement accelerators or other circuits to s...
David Sheldon, Frank Vahid
ISPASS
2008
IEEE
16 years 1 months ago
Configurational Workload Characterization
Although the best processor design for executing a specific workload does depend on the characteristics of the workload, it can not be determined without factoring-in the effect o...
Hashem Hashemi Najaf-abadi, Eric Rotenberg
AINA
2007
IEEE
16 years 1 months ago
How to Study Wireless Mesh Networks: A hybrid Testbed Approach
— Simulation is the most famous way to study wireless an mobile networks since they offer a convenient combination of flexibility and controllability. However, their largest dis...
Alexander Zimmermann, Mesut Günes, Martin Wen...
CODES
2007
IEEE
16 years 1 months ago
Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip
Networks on Chip (NoC) have emerged as the design paradigm for scalable System on Chip communication infrastructure. A growing number of applications, often with firm (FRT) or so...
Andreas Hansson, Martijn Coenen, Kees Goossens
« Prev « First page 2726 / 3031 Last » Next »