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LCPC
2004
Springer
16 years 3 days ago
Phase-Based Miss Rate Prediction Across Program Inputs
Previous work shows the possibility of predicting the cache miss rate (CMR) for all inputs of a program. However, most optimization techniques need to know more than the miss rate ...
Xipeng Shen, Yutao Zhong, Chen Ding
SCOPES
2004
Springer
16 years 3 days ago
An Automated C++ Code and Data Partitioning Framework for Data Management of Data-Intensive Applications
An automated framework for code and data partitioning for the needs of data management is presented. The goal is to identify the main data types from the data management perspectiv...
Athanasios Milidonis, Grigoris Dimitroulakos, Mich...
INFOCOM
2003
IEEE
16 years 1 days ago
Physical Topology Discovery for Large Multi-Subnet Networks
— Knowledge of the up-to-date physical (i.e., layer-2) topology of an Ethernet network is crucial to a number of critical network management tasks, including reactive and proacti...
Yigal Bejerano, Yuri Breitbart, Minos N. Garofalak...
IPPS
2003
IEEE
16 years 1 days ago
Leveraging Block Decisions and Aggregation in the ShareStreams QoS Architecture
ShareStreams (Scalable Hardware Architectures for Stream Schedulers) is a canonical architecture for realizing a range of scheduling disciplines. This paper discusses the design c...
Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten ...
MICRO
2003
IEEE
106views Hardware» more  MICRO 2003»
16 years 20 hour ago
Single-ISA Heterogeneous Multi-Core Architectures: The Potential for Processor Power Reduction
This paper proposes and evaluates single-ISA heterogeneous multi-core architectures as a mechanism to reduce processor power dissipation. Our design incorporates heterogeneous cor...
Rakesh Kumar, Keith I. Farkas, Norman P. Jouppi, P...
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