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HICSS
1995
IEEE
109views Biometrics» more  HICSS 1995»
15 years 10 months ago
The architecture of an optimistic CPU: the WarpEngine
The architecture for a shared memory CPU is described. The CPU allows for parallelism down to the level of single instructions and is tolerant of memory latency. All executable in...
John G. Cleary, Murray Pearson, Husam Kinawi
ISAAC
1995
Springer
135views Algorithms» more  ISAAC 1995»
15 years 10 months ago
The I/O - Complexity of Ordered Binary - Decision Diagram Manipulation
Ordered Binary-Decision Diagrams (OBDD) are the state-of-the-art data structure for boolean function manipulation and there exist several software packages for OBDD manipulation. ...
Lars Arge
VL
1995
IEEE
110views Visual Languages» more  VL 1995»
15 years 10 months ago
Heterogeneous Visual Languages-Integrating Visual and Textual Programming
After more than a decade of research, visual languages have still not become everyday programming tools. On a short term, an integration of visual languages with well-established ...
Martin Erwig, Bernd Meyer
ASPLOS
1991
ACM
15 years 10 months ago
LimitLESS Directories: A Scalable Cache Coherence Scheme
Caches enhance the performance of multiprocessors by reducing network trac and average memory access latency. However, cache-based systems must address the problem of cache coher...
David Chaiken, John Kubiatowicz, Anant Agarwal
SPDP
1991
IEEE
15 years 10 months ago
Local vs. global memory in the IBM RP3: experiments and performance modelling
A number of experiments regarding the placement of instructions, private data and shared data in the Non-Uniform-Memory-Access multiprocessor, RP3 has been performed. Three Scient...
Mats Brorsson
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