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187
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ISCAS
2003
IEEE
16 years 9 days ago
2003
IEEE
Conventional ASIC designs are hard to be customized. Therefore DSP core-based ASIC design has potentially large payoff. This approach not only supports improved performance but al...
242
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ASAP
1996
IEEE
15 years 11 months ago
1996
IEEE
A datapath synthesis system (DPSS) for a bus-based wavefront array architecture, called rDPA (reconfigurable datapath architecture), is presented. An internal data bus to the arra...
256
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ICCAD
1994
IEEE
15 years 11 months ago
1994
IEEE
Interconnectperformance does not scale well into deep submicron dimensions, and the rising number of analog effects erodes tal abstraction necessary for high levels of integration...
193
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ASPDAC
2007
ACM
15 years 11 months ago
2007
ACM
- Next-generation embedded systems in application domains such as multimedia, wired and wireless communications, and multipurpose portable devices, are increasingly turning to mult...
204
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DATE
2004
IEEE
15 years 10 months ago
2004
IEEE
To alleviate the system performance unpredictability of multitasking applications running on multiprocessor platforms with shared memory hierarchies we propose a task level set ba...