12333 search results - page 534 / 2467 » System Level Modelling for Hardware Software Systems |
201
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ICCAD
2003
IEEE
16 years 3 months ago
2003
IEEE
Abstract: In this paper, we present an interprocessor communication-aware task scheduling algorithm applicable to a multiprocessor system executing an application with dependent ta...
207
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QEST
2007
IEEE
16 years 1 months ago
2007
IEEE
Previous studies have shown that buffering packets in DRAM is a performance bottleneck. In order to understand the impediments in accessing the DRAM, we developed a detailed Petri...
226
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IEEEINTERACT
2003
IEEE
16 years 9 days ago
2003
IEEE
Recent studies on program execution behavior reveal that a large amount of execution time is spent in small frequently executed regions of code. Whereas adaptive cache management ...
185
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ESORICS
2008
Springer
15 years 8 months ago
2008
Springer
In this paper, we present the security implications of x86 processor bugs or backdoors on operating systems and virtual machine monitors. We will not try to determine whether the b...
175
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CODES
2006
IEEE
16 years 1 months ago
2006
IEEE
Time-critical multi-processor systems require guaranteed services in terms of throughput, bandwidth etc. in order to comply to hard real-time constraints. However, guaranteedservi...