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IPPS
2009
IEEE
16 years 1 months ago
Using hardware transactional memory for data race detection
Abstract—Widespread emergence of multicore processors will spur development of parallel applications, exposing programmers to degrees of hardware concurrency hitherto unavailable...
Shantanu Gupta, Florin Sultan, Srihari Cadambi, Fr...
FPL
2004
Springer
109views Hardware» more  FPL 2004»
16 years 6 days ago
Hardware Accelerated Novel Protein Identification
The proteins in living organisms perform almost every significant function that governs life. A protein's functionality depends upon its physical structure, which depends on i...
Anish Alex, Jonathan Rose, Ruth Isserlin-Weinberge...
INFOCOM
2005
IEEE
16 years 12 days ago
Connection admission control for flow level QoS in bufferless models
Abstract— Admission control algorithms used in access networks for multiplexed voice sources are typically based on aggregated system characteristics, such as aggregate loss prob...
Sándor Rácz, Tamás Jakabfy, J...
SBACPAD
2007
IEEE
110views Hardware» more  SBACPAD 2007»
16 years 1 months ago
Architectural Breakdown of End-to-End Latency in a TCP/IP Network
Adoption of the 10GbE Ethernet standard has been impeded by two important performance-oriented considerations: 1) processing requirements of common protocol stacks and 2) end-to-e...
Steen Larsen, Parthasarathy Sarangam, Ram Huggahal...
FPL
2006
Springer
103views Hardware» more  FPL 2006»
15 years 10 months ago
A System Design Methodology for Reducing System Integration Time and Facilitating Modular Design Verification
This paper provides a realistic case study of using the previously introduced SIMPPL system architectural model, which fixes the physical interface and communication protocols bet...
Lesley Shannon, Blair Fort, Samir Parikh, Arun Pat...