12333 search results - page 325 / 2467 » System Level Modelling for Hardware Software Systems |
249
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FPGA
2003
ACM
15 years 12 months ago
2003
ACM
This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ...
181
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PLDI
2009
ACM
16 years 1 months ago
2009
ACM
Decentralized information flow control (DIFC) is a promising model for writing programs with powerful, end-to-end security guarantees. Current DIFC systems that run on commodity ...
166
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ENGL
2008
15 years 6 months ago
2008
With the advent of System-On-Chip (SOC) technology, there is a pressing need to enhance the quality of ools available and increase the level of abstraction at which hardware is des...
180
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ICCD
2003
IEEE
16 years 3 months ago
2003
IEEE
Multiple clock domains are a challenge for hardware specification and verification. We present a method for specifying the relations between multiple clocks, and for modeling th...
165
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HOST
2009
IEEE
15 years 4 months ago
2009
IEEE
Abstract-- We report our experiences in designing and implementing several hardware Trojans within the framework of the Embedded System Challenge competition that was held as part ...