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» System Level Modelling for Hardware Software Systems
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PPOPP
2006
ACM
16 years 18 days ago
McRT-STM: a high performance software transactional memory system for a multi-core runtime
Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed t...
Bratin Saha, Ali-Reza Adl-Tabatabai, Richard L. Hu...
IPPS
1998
IEEE
15 years 11 months ago
HOSMII: A Virtual Hardware Integrated with DRAM
WASMII, a virtual hardware system that executes data ow algorithms, is based on an MPLD, an extended FPGA with multiple sets of con guration SRAM. Although we have developed an emu...
Yuichiro Shibata, Hidenori Miyazaki, Xiao-ping Lin...
ACSD
2006
IEEE
102views Hardware» more  ACSD 2006»
15 years 8 months ago
Models of Computation for Networks on Chip
Networks on chip platforms offer the opportunity to introduce a new abstraction level that defines a set of platform services with performance and power characteristics. By making...
Axel Jantsch
FPL
2005
Springer
122views Hardware» more  FPL 2005»
16 years 5 days ago
FPGA-Aware Garbage Collection in Java
— During codesign of a system, one still runs into the impedance mismatch between the software and hardware worlds. er identifies the different levels of abstraction of hardware...
Philippe Faes, Mark Christiaens, Dries Buytaert, D...
CGO
2007
IEEE
16 years 1 months ago
Ubiquitous Memory Introspection
Modern memory systems play a critical role in the performance of applications, but a detailed understanding of the application behavior in the memory system is not trivial to atta...
Qin Zhao, Rodric M. Rabbah, Saman P. Amarasinghe, ...