Sciweavers

12333 search results - page 270 / 2467
» System Level Modelling for Hardware Software Systems
Sort
View
DATE
2003
IEEE
88views Hardware» more  DATE 2003»
15 years 12 months ago
Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues
This paper presents an approach for the integration of reconfigurable hardware and computer applications based on the concept of ubiquitous computing. The goal is to allow a netwo...
Leandro Soares Indrusiak, Florian Lubitz, Ricardo ...
CPE
2000
Springer
369views Hardware» more  CPE 2000»
15 years 11 months ago
Petri Net Modelling and Performability Evaluation with TimeNET 3.0
Abstract. This paper presents TimeNET, a software tool for the modelling and performability evaluation using stochastic Petri nets. The tool has been designed especially for models...
Armin Zimmermann, Jörn Freiheit, Reinhard Ger...
ICASSP
2010
IEEE
15 years 1 months ago
Physical layer algorithm and hardware verification of MIMO relays using cooperative partial detection
Cooperative communication with multi-antenna relays can significantly increase the reliability and speed. However, cooperative MIMO detection would impose considerable complexity o...
Kiarash Amiri, Michael Wu, Melissa Duarte, Joseph ...
CODES
2000
IEEE
15 years 11 months ago
Towards a new standard for system-level design
—Huge new design challenges for system-on-chip (SoC) are the result of decreasing time-to-market coupled with rapidly increasing gate counts and embedded software representing 50...
Stan Y. Liao
IEEEPACT
2007
IEEE
16 years 27 days ago
JudoSTM: A Dynamic Binary-Rewriting Approach to Software Transactional Memory
With the advent of chip-multiprocessors, we are faced with the challenge of parallelizing performance-critical software. Transactional memory (TM) has emerged as a promising progr...
Marek Olszewski, Jeremy Cutler, J. Gregory Steffan