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DATE
2009
IEEE
126views Hardware» more  DATE 2009»
16 years 1 months ago
Fast and accurate protocol specific bus modeling using TLM 2.0
—The need to have Transaction Level models early in the design cycle is becoming more and more important to shorten the development times of complex Systems-on-Chip (SoC). These ...
H. W. M. van Moll, Henk Corporaal, Víctor R...
CASES
2010
ACM
15 years 4 months ago
Hardware trust implications of 3-D integration
3-D circuit-level integration is a chip fabrication technique in which two or more dies are stacked and combined into a single circuit through the use of vertical electroconductiv...
Ted Huffmire, Timothy E. Levin, Michael Bilzor, Cy...
CLUSTER
2007
IEEE
15 years 6 months ago
The computer as software component: A mechanism for developing and testing resource management software
— In this paper, we present an architecture that encapsulates system hardware inside a software component used for job execution and status monitoring. The development of this in...
Narayan Desai, Theron Voran, Ewing L. Lusk, Andrew...
CASES
2006
ACM
16 years 16 days ago
Modeling heterogeneous SoCs with SystemC: a digital/MEMS case study
Designers of SoCs with non-digital components, such as analog or MEMS devices, can currently use high-level system design languages, such as SystemC, to model only the digital par...
Ankush Varma, Muhammad Yaqub Afridi, Akin Akturk, ...
TOMACS
1998
140views more  TOMACS 1998»
15 years 6 months ago
Technical Note: A Hierarchical Computer Architecture Design and Simulation Environment
architectures at multiple levels of abstraction, encompassing both hardware and software. It has five modes of operation (Design, Model Validation, Build Simulation, Simulate Syste...
Paul S. Coe, Fred W. Howell, Roland N. Ibbett, Lau...