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MICRO
2003
IEEE
109views Hardware» more  MICRO 2003»
15 years 12 months ago
TLC: Transmission Line Caches
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
Bradford M. Beckmann, David A. Wood
DAC
2003
ACM
15 years 11 months ago
Determining appropriate precisions for signals in fixed-point IIR filters
This paper presents an analytical framework for the implementation of digital infinite impulse response filters in fixed-point hardware on field programmable gate arrays. This ana...
Joan Carletta, Robert J. Veillette, Frederick W. K...
ISCA
2002
IEEE
105views Hardware» more  ISCA 2002»
15 years 11 months ago
Tarantula: A Vector Extension to the Alpha Architecture
Tarantula is an aggressive floating point machine targeted at technical, scientific and bioinformatics workloads, originally planned as a follow-on candidate to the EV8 processo...
Roger Espasa, Federico Ardanaz, Julio Gago, Roger ...
ICCAD
2000
IEEE
95views Hardware» more  ICCAD 2000»
15 years 11 months ago
Test of Future System-on-Chips
Spurred by technology leading to the availability of millions of gates per chip, system-level integration is evolving as a new paradigm, allowing entire systems to be built on a s...
Yervant Zorian, Sujit Dey, Mike Rodgers
ISCA
1996
IEEE
126views Hardware» more  ISCA 1996»
15 years 10 months ago
Memory Bandwidth Limitations of Future Microprocessors
This paper makes the case that pin bandwidth will be a critical consideration for future microprocessors. We show that many of the techniques used to tolerate growing memory laten...
Doug Burger, James R. Goodman, Alain Kägi
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