452 search results - page 66 / 91 » System Level Hardware-Software Design Exploration with XCS |
182
click to vote
TCAD
2008
15 years 5 months ago
2008
Soft-error induced reliability problems have become a major challenge in designing new generation microprocessors. Due to the on-chip caches' dominant share in die area and tr...
252
click to vote
DAC
2009
ACM
16 years 7 months ago
2009
ACM
Efficient system-level design is increasingly relying on hierarchical design-space exploration, as well as compositional methods, to shorten time-to-market, leverage design re-use...
184
click to vote
FDL
2003
IEEE
15 years 11 months ago
2003
IEEE
Reconfigurable Systolic Arrays are a generalization of Systolic Arrays where node operations and interconnections can be redefined even at run time. This flexibility increases the...
144
click to vote
IV
2003
IEEE
15 years 11 months ago
2003
IEEE
This paper describes a visualisation tool, VlUM, designed to support users in scrutinising models of their interests, preferences and knowledge. We also describe MECUREO, a tool f...
147
click to vote
ICCD
2006
IEEE
16 years 2 months ago
2006
IEEE
— As the geometries of the transistors reach the physical limits of operation, one of the main design challenges of Systems-on-Chips (SoCs) will be to provide dynamic (run-time) ...