28244 search results - page 5362 / 5649 » System Design for Flexibility |
178
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HIPEAC
2007
Springer
16 years 26 days ago
2007
Springer
In a dynamic reordering superscalar processor, the front-end fetches instructions and places them in the issue queue. Instructions are then issued by the back-end execution core. T...
200
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HIPEAC
2007
Springer
16 years 26 days ago
2007
Springer
Abstract. Network processors are programmable devices that can process packets at a high speed. A network processor is typified by multithreading and heterogeneous multiprocessing...
157
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JSSPP
2007
Springer
16 years 26 days ago
2007
Springer
The number of distributed high performance computing architectures has increased exponentially these last years. Thus, systems composed by several computational resources provided ...
195
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LCTRTS
2007
Springer
16 years 26 days ago
2007
Springer
The Instruction Register File (IRF) is an architectural extension for providing improved access to frequently occurring instructions. An optimizing compiler can exploit an IRF by ...
202
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OOPSLA
2007
Springer
16 years 25 days ago
2007
Springer
Omniscient debuggers make it possible to navigate backwards in time within a program execution trace, drastically improving the task of debugging complex applications. Still, they...