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ISCA
2012
IEEE
243views Hardware» more  ISCA 2012»
13 years 9 months ago
BlockChop: Dynamic squash elimination for hybrid processor architecture
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
Jason Mars, Naveen Kumar
SCAM
2005
IEEE
16 years 10 days ago
Control Flow Graph Reconstruction for Assembly Language Programs with Delayed Instructions
Most software for embedded systems, including digital signal processing systems, is coded in assembly language. For both understanding the software and for reverse compiling it to...
Nerina Bermudo, Andreas Krall, R. Nigel Horspool
141
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ICCS
2003
Springer
15 years 12 months ago
Computational Science Simulations Based on Web Services
Abstract. We describe the software architecture of a system for doing multiphysics simulation of a coupled fluid, thermal, and mechanical fracture problem. The system is organized...
L. Paul Chew, Nikos Chrisochoides, S. Gopalsamy, G...
CODES
1996
IEEE
15 years 11 months ago
Partitioning and Exploration Strategies in the TOSCA Co-Design Flow
The TaSCA environment for hardware/software co-design of control dominated systems implemented on a single chip includes a novel approach to the system exploration phase for the e...
Alessandro Balboni, William Fornaciari, Donatella ...
ICSM
1996
IEEE
15 years 11 months ago
Using Informal and Formal Techniques for the Reverse Engineering of C Programs
Reverse engineering of program code is the process of constructing a higher level abstraction of an implementation in order to facilitate the understanding of a system that may be...
Gerald C. Gannod, Betty H. C. Cheng