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ISSS
1999
IEEE
131views Hardware» more  ISSS 1999»
15 years 11 months ago
Compressed Code Execution on DSP Architectures
Decreasing the program size has become an important goal in the design of embedded systems target to mass production. This problem has led to a number of efforts aimed at designin...
Paulo Centoducatte, Ricardo Pannain, Guido Araujo
ASPDAC
1998
ACM
105views Hardware» more  ASPDAC 1998»
15 years 11 months ago
Techniques for Functional Test Pattern Execution
Functional debugging often dominates the time and cost of the ASIC system development, mainly due to the limited controllability and observability of the storage elements in desig...
Inki Hong, Miodrag Potkonjak
ICCAD
1997
IEEE
97views Hardware» more  ICCAD 1997»
15 years 11 months ago
Low power logic synthesis for XOR based circuits
An abundance of research e orts in low power logic synthesis have so far been focused on and or or nand nor based logic. A typical approach is to rst generate an initial multi-lev...
Unni Narayanan, C. L. Liu
UML
1998
Springer
15 years 11 months ago
Automating the Synthesis of UML StateChart Diagrams from Multiple Collaboration Diagrams
The use of scenarios has become a popular technique for requirements elicitation and specification building. Since scenarios capture only partial descriptions of system behavior, ...
Ismaïl Khriss, Mohammed Elkoutbi, Rudolf K. K...
ITC
1996
IEEE
127views Hardware» more  ITC 1996»
15 years 11 months ago
Altering a Pseudo-Random Bit Sequence for Scan-Based BIST
This paper presents a low-overhead scheme for built-in self-test of circuits with scan. Complete (100%) fault coverage is obtained without modifying the function logic and without...
Nur A. Touba, Edward J. McCluskey