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FPL
2009
Springer
132views Hardware» more  FPL 2009»
15 years 10 months ago
Binary Synthesis with multiple memory banks targeting array references
High-Level Synthesis (HLS) is the field of transforming a high-level programming language, such as C, into a register transfer level(RTL) description of the design. In HLS, Binary...
Yosi Ben-Asher, Nadav Rotem
ALGOSENSORS
2006
Springer
15 years 10 months ago
Efficient Training of Sensor Networks
Abstract. Due to their small form factor and modest energy budget, individual sensors are not expected to be GPS-enabled. Moreover, in most applications, exact geographic location ...
Alan A. Bertossi, Stephan Olariu, Maria Cristina P...
EURODAC
1995
IEEE
130views VHDL» more  EURODAC 1995»
15 years 10 months ago
Semi-dynamic scheduling of synchronization-mechanisms
This paper presents a novel approach to scheduling of hardware supported synchronization operations. The optimization goal is to minimize the interation time of processes and thus...
Wolfgang Ecker
BPM
2008
Springer
142views Business» more  BPM 2008»
15 years 8 months ago
Towards Process Models for Disaster Response
In the immediate aftermath of a disaster routine processes, even if specifically designed for such a situation, are not enacted blindly. Actions and processes rather adapt their be...
Dirk Fahland, Heiko Woith
FDL
2008
IEEE
15 years 8 months ago
RTL Generation of Channel Architecture Templates for a Template-based SoC Design Flow
In this paper, we propose the design methodology for communication channel templates from formal specification to RTL description. In this flow, design and verification start from...
Jinhyun Cho, Soonwoo Choi, Soo Chae