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» Synthesis of Reversible Logic
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MSE
2005
IEEE
150views Hardware» more  MSE 2005»
15 years 11 months ago
A Cohesive FPGA-Based System-on-Chip Design Curriculum
A graduate-level computer engineering course sequence at the OGI School of Science and Engineering teaches state-of-the-art digital system design practices and system-on-chip desi...
John D. Lynch, Daniel Hammerstrom, Roy Kravitz
VTS
2005
IEEE
116views Hardware» more  VTS 2005»
15 years 11 months ago
Closed-Form Simulation and Robustness Models for SEU-Tolerant Design
— A closed-form model for simulation and analysis of voltage transients caused by single-event upsets (SEUs) in logic circuits is described. A linear RC model, derived using a SP...
Kartik Mohanram
DAC
1996
ACM
15 years 10 months ago
Delay Minimal Decomposition of Multiplexers in Technology Mapping
Technology mapping requires the unmapped logic network to be represented in terms of base functions, usually two-input NORs and inverters. Technology decomposition is the step tha...
Shashidhar Thakur, D. F. Wong, Shankar Krishnamoor...
ATAL
1995
Springer
15 years 9 months ago
Time, Knowledge, and Choice
Abstract. This article considers the link between theory and practice in agentoriented programming. We begin by rigorously defining a new formal specification language for autono...
Michael Wooldridge
ASPDAC
2009
ACM
111views Hardware» more  ASPDAC 2009»
16 years 21 days ago
A UML-based approach for heterogeneous IP integration
- With increasing availability of predefined IP (Intellectual Properties) blocks and inexpensive microprocessors, embedded system designers are faced with more design choices than ...
Zhenxin Sun, Weng-Fai Wong