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DATE
2000
IEEE
110views Hardware» more  DATE 2000»
15 years 10 months ago
Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery Circuits
Clock and data recovery circuits are essential components in communication systems. They directly influence the bit-error-rate performance of communication links. It is desirable...
Alper Demir, Peter Feldmann
CSCW
1996
ACM
15 years 10 months ago
Supporting Multi-User, Multi-Applet Workspaces in CBE
Our experience with Internet-based scientific collaboratories indicates that they need to be user-extensible, allow users to add tools and objects dynamically to shared workspaces...
Jang Ho Lee, Atul Prakash, Trent Jaeger, Gwobaw Wu
EMSOFT
2007
Springer
15 years 10 months ago
Necessary and sufficient conditions for deterministic desynchronization
Synchronous reactive formalisms associate concurrent behaviors to precise schedules on global clock(s). This allows a non-ambiguous notion of "absent" signal, which can ...
Dumitru Potop-Butucaru, Robert de Simone, Yves Sor...
DATE
2004
IEEE
126views Hardware» more  DATE 2004»
15 years 10 months ago
Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock Architectures
Latency-insensitive systems were recently proposed by Carloni et al. as a correct-by-construction methodology for single-clock system-on-a-chip (SoC) design using predesigned IP b...
Montek Singh, Michael Theobald
CRYPTO
2006
Springer
159views Cryptology» more  CRYPTO 2006»
15 years 10 months ago
Asymptotically Optimal Two-Round Perfectly Secure Message Transmission
Abstract. The problem of perfectly secure message transmission concerns two synchronized non-faulty processors sender (S) and receiver (R) that are connected by a synchronous netwo...
Saurabh Agarwal, Ronald Cramer, Robbert de Haan